Job Information
Nvidia SRAM Timing Engineer in Santa Clara, California
Today, we are tapping into the unlimited potential of AI to define the next era of computing. An era in which NVIDIA’s GPUs act as the brains of computers, robots, and self-driving cars that can understand the world. Doing what has never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you will be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join our dynamic team and see how you can make a lasting impact on the world!
We are currently looking for a SRAM Timing Engineer to join our team of dedicated engineers developing custom SRAM circuits that help power NVIDIA’s next generation of AI chips.
What you will be doing:
Drive robust methodology for timing analysis of custom circuit IP.
Support SRAM and other custom circuit design engineers through successful timing convergence towards tape-out.
Work closely with design and CAD teams to develop the infrastructure for timing closure, identify improvements and solutions and deploy newer features.
Lead implementation of STA solutions for multiple circuit design and technology teams and 3rd party EDA tool vendors across geographies.
What we need to see:
MS in Computer Science/Engineering, Electrical Engineering or equivalent experience.
Minimum of 6+ years of circuit design and/or timing closure experience with successful tapeouts.
Expertise in Static Timing Analysis and prior working experience with STA tools like NanoTime/PrimeTime.
Thorough understanding of noise, cross talk, OCV effects and Liberty file formats.
Good programming skills in multiple languages (Bash, TCL, Python, Makefile or other scripting languages).
Self-starter with passion for growth, real enthusiasm for continuous learning and sharing findings across the team.
Ways to stand out from the crowd:
Experience working with industry standard EDA tools like HSPICE and NanoTime/PrimeTime.
Previous experience working in custom circuit teams is a definite plus.
Background in debugging and analyzing timing constraints, timing closure of DFT modes such as scan and BIST, statistical variation analysis, spice and ERC flows.
Experience in evaluating CAD products and driving EDA vendors to meet the team’s requirements.
NVIDIA is a pioneer in bringing groundbreaking technology to new markets. We have some of the most forward-thinking and hardworking people in the world working with us. If you are creative and autonomous, we want to hear from you!
The base salary range is 164,000 USD - 304,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
You will also be eligible for equity and benefits (https://www.nvidia.com/en-us/benefits/) . NVIDIA accepts applications on an ongoing basis.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
