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Sr. Physical Design Engineer

Job Number: 354330

Category: Design Engineering

Description: Job Title: Sr. Physical Design Engineer

Pay rate: $66.34 /hr.

Location: Palo Alto, CA

Zip Code: 94304

Start Date: Right Away

Keywords: #PaloAltoJobs; #PhysicalDesignEngineerjobs;

Job Description:

As a Sr. physical design engineer, you will contribute to all design phases of physical design of high performance SoC design at both the block and sub chip levels, as well as the full-chip level from RTL to GDSII. You will collaborate with the Foundry Process Engineer, SoC Architect, Microarchitecture, Packaging, Signal Integrity and Power Integrity teams to drive the overall Physical Design aspects, leading to a successful tape out and production silicon.

Key Qualifications include (but not limited to):

Extensive physical design experiences at both the block level and sub chip level, as well as full-chip level is a plus.

Deep knowledge in physical design, including physical aware synthesis, floor planning, clock tree implementation, routing, STA timing signoff, and chip-finishing.

Good knowledge of basic soc architecture. Be able to work with Front-end design team to address timing, congestion and power issues.

In-Depth Knowledge of design flow from RTL to GDSII.

Good knowledge of EM-IR sign-off requirements.

Experience in using EDA tools like Synopsys (/Cadence) for PPA optimization.

Good script skills such as perl/tcl.

Responsibilities include (but not limited to):

Perform sub chip level and block level place and route, and close design to meeting performance, power and area.

Lead and Perform all aspects of full chip SoC integration activities: die size optimization, floor planning, hard IP integration, partitioning, chip level clock planning, bump placement / RDL routing, power grid generation, full chip STA timing, DFT strategy planning, and final physical verification.

Good knowledge of timing analysis, power analysis, physical verification (DRC/LVS), and formal verification

Working knowledge of UPF specification in Power Intent design, implementation, and verification of power gating, level shifter, and isolation.

Define EM-IR signoff requirements and sign-off methodology.

Define and support Static and Dynamic, thermal, electro-migration, peak current, di/dt, and effective resistance analysis

Develop and support Chip-package-Co-Analysis (CPA) and Chip-Power-Model (CPM) on- die model for package & die co-design analysis

Be an EM-IR sign-off lead with successful tape out track records

Excellent hand-on experience in voltage drop analysis using redhawk or redhawk-SC

Excellent hand-on experience and debugging skills of finding root cause of voltage drop and EM issues

Solid background in EM-IR fundamentals, analytical aptitude and excellent attention to detail

Client Confidential

Work closely with the Foundry Engineer and Microarchitecture team to establish logic levels, Multi-Vt library mixes and choices of tracks, metal-stackup, etc.

Define flows through various EDA tools and write scripts for automation for floor planning, placement, routing, crosstalk avoidance, judicious usage of cell libraries and physical verification

Work with the Microarchitecture, Signal Integrity, Power Integrity and Thermal team to ensure that the floorplan and the logic is designed in such a way such that the Substrate/Packaging and Board Layout and the Power Delivery comprehend the power domains, multiple voltages, power integrity requirements, power gating, specify power sequencing to eliminate leakage paths, always-on power, minimize hot-spots, etc.

Design the floorplan to ensure that the power distribution for the chip for the various voltage domains is consistent with the bump and bump-ball map to ensure power integrity (i.e., minimize voltage droop, utilization of local LDOs) and signal integrity (e.g., aggressor nets)

Ensure that the clocking architecture is robust and meets the timing requirements - i.e., well versed in Clock Tree Synthesis, Static Timing Analysis, Timing closure methodologies, Clock gating, reference clocks, PLL placement, clock mixing, etc.

Well versed in parasitic extraction, LVS/DRC and other verification checks - Physical, Power, Post-Layout Timing

Other Qualifications:

At least 15-20 years of experience in the chip industry with a track record of delivering silicon into volume production across multiple technology generations

Proven track record of SoC definition of complex SoCs over multiple technology generations

BS/MS/PhD in Electrical and Computer Engineering with emphasis on Computer Architecture

Experienced in CPU Architecture - preferably Instruction Decode or Execution Units

Experience in Multi SoC systems is a plus

Knowledge of Machine Learning Algorithms (e.g., Convolutional Neural Networks) is a huge plus

Exhibits the right teamwork and leadership qualities backed up with references

If you are interested in this role, please apply via the apply now link provided. Our overriding goal is to provide quality staffing solutions that help people, organizations, and communities succeed. Belcan is a leading provider of qualified personnel to many of the world's most respected enterprises. We offer excellent opportunities for contract, temporary, temp-to-hire, and direct assignments. We are the employer of choice for thousands worldwide. For more information, please visit our website at Belcan.com

EOE/F/M/D/V

Location: Palo Alto , CA

Minimum Experience (yrs):

Required Education: Not Specified

Benefits:

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