Job Information
PDS Defense FPGA Design/Verification Engineer in Littleton, Colorado
Engineering
FPGA Design/Verification Engineer Littleton, CO Posted: 12/19/2024
Job Description
Job ID#:
209190
Job Category:
Engineering
Position Type:
Associate - W2
Duration:
26
Shift:
1
Positions Available:
3
PDS Defense, Inc. is seeking a FPGA Design/Verification Engineer, in Littleton/Waterton, CO. Job ID#209190
Pay Rate: $89.13 - $110.00/hr
Job Description:
As an ASIC & FPGA DESIGN ENGINEER you will have the opportunity to support over 50 different programs and research and development (R&D) efforts. Your work will affect technology across military space, civil space, commercial space, missiles, missile defense platforms, satellite surveillance platforms, deep space exploration, and manned flight missions.
DAILY FUNCTIONS:
Work with low SWaP, radiation hardened, space rated devices.
Develop RTL/VHDL code, scripts, and other items required for the development of FPGAs, complete design and development, and provide self-test designer level testbench. Collaborate with the LM engineering team to debug or simulate Circuitware with Xilinx development tools, deliver FPGA RTL source code changes, test data and documentation as needed. Work with systems engineers and design engineers to develop concept of operations, design requirements, and assist verification engineers in the verification of FPGA designs. Attend team meetings and reviews as needed. Complete or contribute to the design documentation in accordance with Lockheed Martin processes, All data and drawings must remain exclusively on Lockheed Martin Space internal networks or computing resources and protected according to guidance or training provided by Lockheed Martin.
REQUIREMENTS:
*Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
*Experience in the design of FPGA and/or ASIC devices.
*HDL programming experience with VHDL, Verilog, and/or SystemVerilog.
*US Citizenship is required for this position.
*Experience in the design of FPGA and/or ASIC devices.
*Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
*Experienced in scripting such as Perl, TCL, Python.
*Experience developing test cases based off given requirements.
*Experience building test benches for FPGA / ASIC designs to provide randomized stimulus.
*Knowledge of space-grade/qualified FPGAs and ASICs.
*Must be local to either the Sunnyvale, CA; Valley Forge(King Of Prussia, PA) or Denver, CO area and willing to come in to the site as needed.
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
Job Requirements
Minimum Security Clearance:
No Clearance
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
The California Fair Chance Act
Los Angeles City Fair Chance Ordinance
Los Angeles County Fair Chance Ordinance for Employers
San Francisco Fair Chance Ordinance
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
