Easter Seals Jobs

Microsoft Silicon, Cloud, Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to develop new generation silicon is of paramount importance. To achieve this goal, Microsoft’s Cloud Compute Development Organization (CCDO) is seeking a Physical Design (PD) CPU/High performance Intellectual Property (IP) design Lead/Engineer who is technically driven to join our silicon hardware physical design team, covering leadership, Register Transfer Level (RTL)to design ownership. We are responsible for delivering cutting-edge, High performance Central Processing Unit (CPU) & Custom Accelerator based in-house System on Chip (SOC) designs, which is instrumental in advancing Azure's server-class product roadmap. This team will be involved in numerous projects within Microsoft developing SOC silicon for Azure data centers.

We are looking for a Director Physical Design Engineer to join the team.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Responsibilities

• Manage & Lead a Physical Design team responsible for RTL to GDS2 implementation for IPs , sub-chips/sub-systems and/or SOC level design (in latest tech node).

• Manage direct reports through goal setting, mentoring, coaching, career planning, and assessing performance.

• Coordinate with CAD, RTL/Design teams, Architecture team, Power& Performance team, Package team, Technology team & other internal/external partners.

• Lead & Influence in TFM (Tools, Flows, and Methodology) & PPAS (Power, Performance, Area & Schedule) for design construction to signoff.

• Demonstrate technical expertise across various domains of Physical Design & Timing Signoff (E2E).

• Clear communications on project status & planning.

• Collaborate across various geographic locations based on need.

People Management

• Managers deliver success through empowerment and accountability by modeling, coaching, and caring.

• Model - Live our culture; Embody our values; Practice our leadership principles.

• Coach - Define team objectives and outcomes; Enable success across boundaries; Help the team adapt and learn.

• Care - Attract and retain great people; Know each individual’s capabilities and aspirations; Invest in the growth of others.

Embody our Culture (https://careers.microsoft.com/v2/global/en/culture) & Values (https://www.microsoft.com/en-us/about/corporate-values)

Qualifications

Required Qualifications

• 9+ years of related technical engineering experience

• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experience

• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience

• OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience.

• 8+ years of experience in semiconductor production design tapeouts & implementing designs through synthesis, floor-planning, place and route, extraction, timing, EMIR closure and physical verification.

• 5 + years of experience in a technical leadership role or manager

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred:

• Experience managing a Physical Design/STA team, providing career planning, performance feedback and appraisals, and compensation recommendations.

• Physical Design program management experience includes planning and tracking execution, mitigating discovery, and communicating progress.

• Demonstrated expertise in coaching, collaboration, influencing, and energizing a team via effective written and verbal communication skills.

• Effective project management skills and ability to juggle multiple projects at once.

• Proven understanding of PD construction & analysis flows and methodology.

• Shown ability to execute stringent schedule, PPA targets & die size requirements.

• Effective ommunication, collaboration, teamwork skills and ability to contribute to diverse and inclusive teams.

• Proven track record of implementing designs through synthesis, floor-planning, place and route, extraction, timing, and physical verification.

• Understanding of constraints generation, DFT timing modes, STA analysis, Timing optimization, and Timing closure.

• In-depth understanding of design tradeoffs for Power, Performance, and Area (PPA).

• Share past or present hands-on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.

• Experience in EDA tools such as Primetime, StarRC, Cadence and/or Synopsys PnR tools etc.

• Experience and knowledge of formal equivalency checks, LP, UPF, reliability, SI, and noise analysis.

• problem-solving and data analysis skills.

• Technically leading/guiding a team of multiple PD engineers in order to deliver a Sub-Chip/SoC will be a big plus.

Silicon Engineering M5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until September 3, 2024.

#Siliconjobs #CCDO

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .