Easter Seals Jobs

Description

Acara Solutions is seeking an ASIC and Mixed Signal Design Engineerto join our client located in Colorado Springs on a Remote work opportunity. This is a salaried direct remote position - $167,000 - $213,000 annually.

There are two openings: A 'Principle' level IV working on the back end ($130K - $160K) and a 'Master' Level VI position that is a customer facing position that is also working on the back end. Both need to be strong in design, clocks and corners and good with collaborating with the team.

The position requires recent use of Synopsys products.

Provide technical leadership for new Digital and Mixed-signal ASIC programs. Collaborate with external and internal customers to define ASIC solution architectures. Review and edit target specifications, translating them into design constraints. Implement digital designs using RTL & Logic Synthesis methods (Verilog, VHDL, SystemVerilog). Develop architectures and specifications for complex design blocks. Add DFT (Design for Test) logic for efficient testing during manufacturing. Interface with ASIC customers and internal Place & Route Engineers for correct silicon implementation. Develop verification plans, simulation environments, and perform design verification for digital blocks and systems. Use modern verification methods like directed/random testing, assertions, UVM, and code coverage. Utilize Static Timing Analysis and Formal Verification tools for gate-level correctness. Address ElectroMigration/IR drop analysis impacts on design. Contribute to cost estimates for new ASIC opportunities. Stay current with EDA tools, modern design techniques, and interfaces. Collaborate with customers to develop technical solutions for new missions. Deliver technical report-outs to peers and external customers. Create and execute mixed-signal modeling and simulation. Support and lead project planning and Agile development. Lead proposal estimation and technical write-ups for new program pursuits

Job Requirements

Required Skills / Qualifications: Bachelors Degree in Engineering 10 years minimum experience implementing ASIC or FPGA designs using Verilog/SystemVerilog/VHDL. Recent versions/use of Synopsys products required. Min 2 years of timing analysis, ideally with PrimeTime (Tempus, Optimus and others acceptable). US Citizenship

Preferred Skills / Qualifications: Experience working on proposals with the sales team Spacecraft radiation experience Strong aptitude to learn and apply best practices and techniques using EDA tools. Able to decompose a complex set of product requirements into an execution plan. Experience with computer architectures, computer systems, signal integrity, component selection would be a plus

Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct) are Equal Employment Opportunity and Affirmative Action Employers. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender identity, sexual orientation, national origin, genetic information, sex, age, disability, veteran status, or any other legally protected basis. The Aleron companies welcome and encourage applications from diverse candidates, including people with disabilities. Accommodations are available upon request for applicants taking part in all asp

Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status.

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Aleron companies; Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, Viaduct, and Aleron's strategic partner, SDI are Equal Employment Opportunity and Affirmative Action Employers. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender identity, sexual or entation, national origin, genetic information, sex, age, disability, veteran status, or any other legally protected basis.