Easter Seals Jobs

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or equivalent practical experience.

• 4 years of experience with RTL design using Verilog/System Verilog and microarchitecture.

• 4 years of experience in ARM-based SoCs, interconnects and ASIC methodology.

Preferred qualifications:

• Master’s degree in Electrical Engineering or Computer Engineering.

• Experience in cross-domain, including domain validation, design for testing, physical design, and software.

• Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).

• Experience with Memory Controller.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Work on both the IP design and Integration activities including plan tasks, support and hold code and design reviews, contribute to sub-system/chip-level integration.

• Interact closely with architecture team and develop implementation strategies to meet quality, schedule, and power performance area for IPs.

• Interact closely with the subsystem team and plan SOC milestones, plan quality checks as part of SOC milestones (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc).

• Work closely with the cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and represent project status throughout the development process.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.