Easter Seals Jobs

CAD ML Timing Optimization Engineer

Beaverton,Oregon,United States

Hardware

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor and system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. We invite you to help deliver the next groundbreaking Apple products! In this highly visible role as a key technical member of the Design Methodology and Tools team, you are an integral part of the effort to improve the performance of Apple silicon. You will be responsible for delivering industry-leading solutions for design optimization, design closure, and visualization. Combining machine learning algorithm application with practical design know-how and software engineering best practices, you will help to differentiate and streamline Apple’s silicon engineering methods.

Description

As a CAD ML Timing Optimization Engineer, you will: - Deliver methodology and tool solutions for static timing closure and power optimization. - Apply data science and ML analytics to quantify, mine, and predict intriguing patterns. - Deploy innovative modeling and optimization approaches to achieve globally optimal targets. - Prudently apply best-in-class learning algorithms to deliver value-adding design solutions. - Pursue deep analysis of design implementation alternatives to isolate key issues and identify appropriate ECO remedies. - Implement code infrastructure to facilitate analytics and visualization. - Collaborate with silicon design, CAD, and EDA partners to identify flow deficiencies and enact creative solutions.

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience.

• Software engineering background using Python and C++.

• Experience in applying ML and/or GPU accelerated approaches to problems.

• Prior usage of optimization algorithms, data modeling, and graphs.

Key Qualifications

Preferred Qualifications

• Hands on experience in static timing analysis and/or design optimization flows.

• Familiarity with timing and power ECO techniques for high performance processor designs.

• Solid understanding of Physical Design challenges, proficiency with place and route tools and implementation exploration.

• Experience using a variety of deep learning libraries and infrastructure.

• Strong analytical skills and ability to identify and communicate high ROI opportunities.

Education & Experience

Additional Requirements

• Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant. (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf)

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Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (Opens in a new window) .

Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. United States Department of Labor. Learn more (Opens in a new window) .

Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you’re applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines (opens in a new window) applicable in your area.

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