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Staff ASIC & FPGA Design Engineer (HYBRID TELEWORK)

Lockheed Martin - King of Prussia, Pennsylvania
ASIC & FPGA Design Engineer - Vitis HLS (HYBRID TELEWORK)

Lockheed Martin - King of Prussia, Pennsylvania
ASIC Engineer, Design

Meta - Austin, Texas
ASIC Engineer, Design

Meta - Sunnyvale, California
ASIC Design Verification Engineer (ASIC / Hardware)

Palo Alto Networks - Santa Clara, California
ASIC & FPGA Design Engineering

Actalent - Orlando, Florida
CAD Infrastructure Engineer for ASIC Design

Capgemini - San Jose, California
Senior ASIC Design Engineer

Cisco - San Jose, California
ASIC & FPGA Design Engineer / Syracuse, NY

Lockheed Martin - Liverpool, New York
ASIC Design Engineer, Core IP

Google - Mountain View, California
ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

Amazon - Austin, Texas
ASIC Design Engineer - Neural Engine DMA

Apple - Cupertino, California
Senior Principal Digital Engineer (FPGA and ASIC Design)

Northrop Grumman - Baltimore, Maryland
ASIC Design Engineer - Hardware

Nvidia - Austin, Texas
ASIC & FPGA Design Engineer Sr Staff

Lockheed Martin - Owego, New York
ASIC Design Engineer, Technical Leader

Cisco - San Jose, California
ASIC Design Engineer, Senior Technical Leader

Cisco - San Jose, California
Senior ASIC Design Engineer

Cisco - San Jose, California